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Ultralow Noise VGAs with Preamplifier and Programmable RIN AD8331/AD8332/AD8334
FEATURES
Ultralow noise preamplifier Voltage noise = 0.74 nV/Hz Current noise = 2.5 pA/Hz 3 dB bandwidth AD8331: 120 MHz AD8332, AD8334: 100 MHz Low power AD8331: 125 mW/channel AD8332, AD8334: 145 mW/channel Wide gain range with programmable postamp -4.5 dB to +43.5 dB +7.5 dB to +55.5 dB Low output-referred noise: 48 nV/Hz typical Active input impedance matching Optimized for 10-bit/12-bit ADCs Selectable output clamping level Single 5 V supply operation AD8332 and AD8334 available in lead frame chip scale package
FUNCTIONAL BLOCK DIAGRAM
LON LOP VIP VIN VCM VMID - 48dB ATTENUATOR + 3.5dB/15.5dB VOH 21dB PA VOL CLAMP RCLMP HILO
LNA INH LMD + 19dB -
LNA VCM BIAS
VGA BIAS AND INTERPOLATOR
GAIN CONTROL INTERFACE
ENB
GAIN
Figure 1. Signal Path Block Diagram
60 50 40 VGAIN = 1V VGAIN = 0.8V VGAIN = 0.6V VGAIN = 0.4V VGAIN = 0.2V VGAIN = 0V HIGH GAIN MODE
GAIN (dB)
30 20 10 0 -10 100k
APPLICATIONS
Ultrasound and sonar time-gain controls High performance AGC systems I/Q signal processing High speed, dual ADC drivers
1M
10M FREQUENCY (Hz)
100M
1G
GENERAL DESCRIPTION
The AD8331/AD8332/AD8334 are single-, dual-, and quadchannel ultralow noise, linear-in-dB, variable gain amplifiers (VGAs). Optimized for ultrasound systems, they are usable as a low noise variable gain element at frequencies up to 120 MHz. Included in each channel are an ultralow noise preamplifier (LNA), an X-AMP(R) VGA with 48 dB of gain range, and a selectable gain postamplifier with adjustable output limiting. The LNA gain is 19 dB with a single-ended input and differential outputs. Using a single resistor, the LNA input impedance can be adjusted to match a signal source without compromising noise performance. The 48 dB gain range of the VGA makes these devices suitable for a variety of applications. Excellent bandwidth uniformity is maintained across the entire range. The gain control interface provides precise linear-in-dB scaling of 50 dB/V for control voltages between 40 mV and 1 V. Factory trim ensures excellent part-to-part and channel-to-channel gain matching.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
Figure 2. Frequency Response vs. Gain
Differential signal paths result in superb second- and thirdorder distortion performance and low crosstalk. The VGA's low output-referred noise is advantageous in driving high speed differential ADCs. The gain of the postamplifier can be pin selected to 3.5 dB or 15.5 dB to optimize gain range and output noise for 12-bit or 10-bit converter applications. The output can be limited to a user-selected clamping level, preventing input overload to a subsequent ADC. An external resistor adjusts the clamping level. The operating temperature range is -40C to +85C. The AD8331 is available in a 20-lead QSOP package, the AD8332 is available in 28-lead TSSOP and 32-lead LFCSP packages, and the AD8334 is available in a 64-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
03199-002
03199-001
AD8331/AD8332/AD8334
AD8331/AD8332/AD8334 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance Characteristics ........................................... 12 Test Circuits..................................................................................... 20 Measurement Considerations................................................... 20 Theory of Operation ...................................................................... 24 Overview...................................................................................... 24 Low Noise Amplifier (LNA) ..................................................... 25 Variable Gain Amplifier ............................................................ 27 Postamplifier ............................................................................... 28 Applications..................................................................................... 30 LNA--External Components.................................................... 30 Driving ADCs ............................................................................. 32 Overload ...................................................................................... 32 Optional Input Overload Protection. ...................................... 33 Layout, Grounding, and Bypassing.......................................... 33 Multiple Input Matching ........................................................... 33 Disabling the LNA...................................................................... 33 Ultrasound TGC Application ................................................... 34 High Density Quad Layout ....................................................... 34 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 40
Rev. E | Page 2 of 40
AD8331/AD8332/AD8334
REVISION HISTORY
4/06--Rev. D to Rev. E Added AD8334 ................................................................... Universal Changes to Figure 1 and Figure 2....................................................1 Changes to Table 1 ............................................................................4 Changes to Table 2 ............................................................................7 Changes to Figure 7 through Figure 9 and Figure 12.................12 Changes to Figure 13, Figure 14, Figure 16, and Figure 18 .......13 Changes to Figure 23 and Figure 24 .............................................14 Changes to Figure 25 through Figure 27......................................15 Changes to Figure 31 and Figure 33 through Figure 36.............16 Changes to Figure 37 through Figure 42......................................17 Changes to Figure 43, Figure 44, and Figure 48..........................18 Changes to Figure 49, Figure 50, and Figure 54..........................19 Inserted Figure 56 and Figure 57 ..................................................20 Inserted Figure 58, Figure 59, and Figure 61 ...............................21 Changes to Figure 60 ......................................................................21 Inserted Figure 63 and Figure 65 ..................................................22 Changes to Figure 64 ......................................................................22 Moved Measurement Considerations Section ............................20 Inserted Figure 67 and Figure 68 ..................................................23 Inserted Figure 70 and Figure 71 ..................................................24 Change to Figure 72 ........................................................................24 Changes to Figure 73 and Low Noise Amplifier Section ...........25 Changes to Postamplifier Section .................................................28 Changes to Figure 80 ......................................................................29 Changes to LNA--External Components Section......................30 Changes to Logic Inputs--ENB, MODE, and HILO Section....31 Changes to Output Decoupling and Overload Sections ............32 Changes to Layout, Grounding, and Bypassing Section ............33 Changes to Ultrasound TGC Application Section......................34 Added High Density Quad Layout Section .................................34 Inserted Figure 94............................................................................38 Updated Outline Dimensions........................................................39 Changes to Ordering Guide...........................................................40 3/06--Rev. C to Rev. D Updated Format ................................................................. Universal Changes to Features and General Description..............................1 Changes to Table 1 ............................................................................3 Changes to Table 2 ............................................................................6 Changes to Ordering Guide...........................................................34 11/03--Rev. B to Rev. C Addition of New Part......................................................... Universal Changes to Figures............................................................. Universal Updated Outline Dimensions........................................................32 5/03--Rev. A to Rev. B Edits to Ordering Guide.................................................................32 Edits to Ultrasound TGC Application Section ...........................25 Added Figure 71, Figure 72, and Figure 73..................................26 Updated Outline Dimensions........................................................31 2/03--Rev. 0 to Rev. A Edits to Ordering Guide.................................................................32
Rev. E | Page 3 of 40
AD8331/AD8332/AD8334 SPECIFICATIONS
TA = 25C, VS = 5 V, RL = 500 , RS = RIN = 50 , RFB = 280 , CSH = 22 pF, f = 10 MHz, RCLMP = , CL = 1 pF, VCM pin floating, -4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified. Table 1.
Parameter LNA CHARACTERISTICS Gain Input Voltage Range Input Resistance Conditions Single-ended input to differential output Input to output (single ended) AC-coupled RFB = 280 RFB = 412 RFB = 562 RFB = 1.13 k RFB = Single-ended, either output VOUT = 0.2 V p-p RS = 0 , HI or LO gain, RFB = , f = 5 MHz RFB = , HI or LO gain, f = 5 MHz f = 10 MHz, LOP output RS = RIN = 50 RS = 50 , RFB = VOUT = 0.5 V p-p, single-ended, f = 10 MHz Min Typ 19 13 275 50 75 100 200 6 13 5 130 650 0.74 2.5 3.7 2.5 -56 -70 165 Max Unit dB dB mV k pF MHz V/s nV/Hz pA/Hz dB dB dBc dBc mA
Input Capacitance Output Impedance -3 dB Small Signal Bandwidth Slew Rate Input Voltage Noise Input Current Noise Noise Figure Active Termination Match Unterminated Harmonic Distortion @ LOP1 or LOP2 HD2 HD3 Output Short-Circuit Current LNA + VGA CHARACTERISTICS -3 dB Small Signal Bandwidth AD8331 AD8332, AD8334 -3 dB Large Signal Bandwidth AD8331 AD8332, AD8334 Slew Rate AD8331 AD8332, AD8334 Input Voltage Noise Noise Figure Active Termination Match Unterminated Output-Referred Noise AD8331 AD8332, AD8334 Output Impedance, Postamplifier
Pin LON, Pin LOP VOUT = 0.2 V p-p
120 100 VOUT = 2 V p-p 110 90 LO gain HI gain LO gain HI gain RS = 0 , HI or LO gain, RFB = , f = 5 MHz VGAIN = 1.0 V RS = RIN = 50 , f = 10 MHz, measured RS = RIN = 200 , f = 5 MHz, simulated RS = 50 , RFB = , f = 10 MHz, measured RS = 200 , RFB = , f = 5 MHz, simulated VGAIN = 0.5 V, LO gain VGAIN = 0.5 V, HI gain VGAIN = 0.5 V, LO gain VGAIN = 0.5 V, HI gain DC to 1 MHz 300 1200 275 1100 0.82 4.15 2.0 2.5 1.0 48 178 40 150 1
MHz MHz MHz MHz V/s V/s V/s V/s nV/Hz dB dB dB dB nV/Hz nV/Hz nV/Hz nV/Hz
Rev. E | Page 4 of 40
AD8331/AD8332/AD8334
Parameter Output Signal Range, Postamplifier Differential Output Offset Voltage AD8331 AD8332, AD8334 Output Short-Circuit Current Harmonic Distortion AD8331 HD2 HD3 HD2 HD3 AD8332, AD8334 HD2 HD3 HD2 HD3 Input 1 dB Compression Point Two-Tone Intermodulation Distortion (IMD3) AD8331 AD8332, AD8334 Output Third-Order Intercept AD8331 AD8332, AD8334 Channel-to-Channel Crosstalk (AD8332, AD8334) Overload Recovery Group Delay Variation ACCURACY Absolute Gain Error 2 Conditions RL 500 , unclamped, either pin VGAIN = 0.5 V Differential Common mode Differential Common mode VGAIN = 0.5 V, VOUT = 1 V p-p, HI gain f = 1 MHz f = 10 MHz -88 -85 -68 -65 -82 -85 -62 -66 1 -80 -72 -78 -74 38 33 35 32 -98 5 2 -1 -1 -2 +0.5 0.3 -1 0.2 0.1 50 -4.5 to +43.5 7.5 to 55.5 0 to 1.0 10 500 30 -25 1.5 to 3.5 +2 +1 +1 dBc dBc dBc dBc dBc dBc dBc dBc dBm 1 dBc dBc dBc dBc dBm dBm dBm dBm dB ns ns dB dB dB dB dB dB/V dB dB V M ns mV V Min Typ VCM 1.125 4.5 5 -25 5 -25 45 Max Unit V V p-p mV mV mV mV mA
-50 -125 -20 -125
+50 +100 +20 +100
f = 1 MHz f = 10 MHz VGAIN = 0.25 V, VOUT = 1 V p-p, f = 1 MHz to 10 MHz VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.72 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 10 MHz VGAIN = 0.5 V, VOUT = 1 V p-p, f = 1 MHz VGAIN = 1.0 V, VIN = 50 mV p-p/1 V p-p, f = 10 MHz 5 MHz < f < 50 MHz, full gain range 0.05 V < VGAIN < 0.10 V 0.10 V < VGAIN < 0.95 V 0.95 V < VGAIN < 1.0 V 0.1 V < VGAIN < 0.95 V 0.1 V < VGAIN < 0.95 V 0.10 V < VGAIN < 0.95 V LO gain HI gain
Gain Law Conformance 3 Channel-to-Channel Gain Matching GAIN CONTROL INTERFACE (Pin GAIN) Gain Scaling Factor Gain Range Input Voltage (VGAIN) Range Input Impedance Response Time COMMON-MODE INTERFACE (PIN VCMn) Input Resistance 4 Output CM Offset Voltage Voltage Range
48.5
51.5
48 dB gain change to 90% full scale Current limited to 1 mA VCM = 2.5 V VOUT = 2.0 V p-p
-125
+100
Rev. E | Page 5 of 40
AD8331/AD8332/AD8334
Parameter ENABLE INTERFACE (PIN ENB, PIN ENBL, PIN ENBV) Logic Level to Enable Power Logic Level to Disable Power Input Resistance Conditions Min Typ Max Unit
2.25 0 Pin ENB Pin ENBL Pin ENBV VINH = 30 mV p-p VINH = 150 mV p-p 2.25 0 50 25 40 70 300 4
5 1.0
Power-Up Response Time HILO GAIN RANGE INTERFACE (PIN HILO) Logic Level to Select HI Gain Range Logic Level to Select LO Gain Range Input Resistance OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR LO GAIN) Accuracy HILO = LO HILO = HI MODE INTERFACE (PIN MODE) Logic Level for Positive Gain Slope Logic Level for Negative Gain Slope Input Resistance POWER SUPPLY (PIN VPS1, PIN VPS2, PIN VPSV, PIN VPSL, PIN VPOS) Supply Voltage Quiescent Current per Channel AD8331 AD8332, AD8334 Power Dissipation per channel AD8331 AD8332, AD8334 Power-Down Current AD8332 (VGA and LNA Disabled) AD8331 (VGA and LNA Disabled) LNA Current AD8331 (ENBL) AD8332, AD8334 (ENBL) VGA Current AD8331 (ENBV) AD8332, AD8334 (ENBV) PSRR
1 2
V V k k k s ms V V k
5 1.0
RCLMP = 2.74 k, VOUT = 1 V p-p (clamped) RCLMP = 2.21 k, VOUT = 1 V p-p (clamped) 0 2.25
50 75 1.0 5 200
mV mV V V k
4.5 20 20 No signal
5.0 25 29 125 145
5.5
V mA mA mW mW
50 50 Each channel Each channel 7.5 7.5 7.5 7.5 VGAIN = 0 V, f = 100 kHz
300 240 11 12 14 17 -68
600 400 15 15 20 20
A A mA mA mA mA dB
All dBm values are referred to 50 . The absolute gain refers to the theoretical gain expression in Equation 1. 3 Best-fit to linear-in-dB curve. 4 The current is limited to 1 mA typical.
Rev. E | Page 6 of 40
AD8331/AD8332/AD8334 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Voltage Supply Voltage (VPSn, VPSV, VPSL, VPOS) Input Voltage (INHn) ENB, ENBL, ENBV, HILO Voltage GAIN Voltage Power Dissipation AR Package 1 CP-20 Package (AD8331) CP-32 Package (AD8332) RQ Package1 CP-64 Package (AD8334) Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) JA AR Package1 CP-20 Package 2 CP-32 Package2 RQ Package1 CP-64 Package 3
1 2
Rating 5.5 V VS + 200 mV VS + 200 mV 2.5 V 0.96 W 1.63 W 1.97 W 0.78 W 0.91 W -40C to +85C -65C to +150C 300C 68C/W 40C/W 33C/W 83C/W 24.2C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Four-layer JEDEC board (2S2P). Exposed pad soldered to board, nine thermal vias in pad--JEDEC, 4-layer board J-STD-51-9. 3 Exposed pad soldered to board, 25 thermal vias in pad--JEDEC, 4-layer board J-STD-51-9.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. E | Page 7 of 40
AD8331/AD8332/AD8334 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
LMD INH VPSL LON LOP COML VIP VIN MODE
1 2 3 4 5 6 7 8 9 PIN 1 INDICATOR 20 19 18 17
COMM ENBL ENBV COMM VOL VOH VPOS HILO
03199-003
AD8331
TOP VIEW (Not to Scale)
16 15 14 13 12 11
RCLMP VCM
GAIN 10
Figure 3. 20-Lead QSOP Pin Configuration (AD8331)
Table 3. 20-Lead QSOP Pin Function Description (AD8331)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic LMD INH VPSL LON LOP COML VIP VIN MODE GAIN VCM RCLMP HILO VPOS VOH VOL COMM ENBV ENBL COMM Description LNA Signal Ground LNA Input LNA 5 V Supply LNA Inverting Output LNA Noninverting Output LNA Ground VGA Noninverting Input VGA Inverting Input Gain Slope Logic Input Gain Control Voltage Common Mode Voltage Output Clamping Level Gain Range Select (HI or LO) VGA 5 V Supply Noninverting VGA Output Inverting VGA Output VGA Ground VGA Enable LNA Enable VGA Ground
Rev. E | Page 8 of 40
AD8331/AD8332/AD8334
COM1 VCM1
LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2
1 2 3 4 5 6 7 8 9
PIN 1 INDICATOR
28 LMD1 27 INH1 26 VPS1 25 LON1
32
31
30
29
28
27
26
LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2
03199-004
ENBV
25 24 23 22
ENBL
LOP1
HILO
VIN1
VIP1
1 2 3 4 5 6 7 8 9
AD8332
TOP VIEW (Not to Scale)
24 LOP1 23 COM1 22 VIP1 21 VIN1 20 VCM1 19 HILO 18 ENB 17 VOH1 16 VOL1 15 VPSV
PIN 1 INDICATOR
COMM VOH1 VOL1 VPSV NC VOL2 VOH2 COMM
AD8332
TOP VIEW (Not to Scale)
21 20 19 18 17
GAIN 10 RCLMP 11 VOH2 12 VOL2 13 COMM 14
10
11
12
13
14
15
16
LOP2
VIP2
MODE
COM2
GAIN
VIN2
RCLMP
VCM2
NC = NO CONNECT
Figure 4. 28-Lead TSSOP Pin Configuration (AD8332)
Figure 5. 32-Lead LFCSP Pin Configuration (AD8332)
Table 4. 28-Lead TSSOP Pin Function Description (AD8332)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM VPSV VOL1 VOH1 ENB HILO VCM1 VIN1 VIP1 COM1 LOP1 LON1 VPS1 INH1 LMD1 Description CH2 LNA Signal Ground CH2 LNA Input CH2 Supply LNA 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Control Voltage Output Clamping Resistor CH2 Noninverting VGA Output CH2 Inverting VGA Output VGA Ground (Both Channels) VGA Supply 5 V (Both Channels) CH1 Inverting VGA Output CH1 Noninverting VGA Output Enable--VGA/LNA VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground
Table 5. 32-Lead LFCSP Pin Function Description (AD8332)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic LON1 VPS1 INH1 LMD1 LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 MODE GAIN RCLMP COMM VOH2 VOL2 NC VPSV VOL1 VOH1 COMM ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 Description CH1 LNA Inverting Output CH1 LNA Supply 5 V CH1 LNA Input CH1 LNA Signal Ground CH2 LNA Signal Ground CH2 LNA Input CH2 LNA Supply 5 V CH2 LNA Inverting Output CH2 LNA Noninverting Output CH2 LNA Ground CH2 VGA Noninverting Input CH2 VGA Inverting Input CH2 Common-Mode Voltage Gain Slope Logic Input Gain Control Voltage Output Clamping Level Input VGA Ground CH2 Noninverting VGA Output CH2 Inverting VGA Output No Connect VGA Supply 5 V CH1 Inverting VGA Output CH1 Noninverting VGA Output VGA Ground VGA Enable LNA Enable VGA Gain Range Select (HI or LO) CH1 Common-Mode Voltage CH1 VGA Inverting Input CH1 VGA Noninverting Input CH1 LNA Ground CH1 LNA Noninverting Output
Rev. E | Page 9 of 40
03199-005
AD8331/AD8332/AD8334
CLMP12 GAIN12 COM1X COM2 COM1 VCM1 VCM2 LMD1 LON1 LOP1 VPS1 EN12 EN34 INH1 VIN1 VIP1
INH2 LMD2 COM2X LON2 LOP2 VIP2 VIN2 VPS2 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN 1 INDICATOR 48 47 46 45 44 43
COM12 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 MODE NC COM34 VOH3 VOL3 VPS34 VOL4 VOH4 COM34
AD8334
TOP VIEW (Not to Scale)
42 41 40 39 38 37 36 35 34 33
LON4
LOP4
COM3
COM4
LMD4
COM4X
VPS4
HILO
VIP4
INH4
VIN4
VCM4
GAIN34
CLMP34
VCM3
NC
NC = NO CONNECT
Figure 6. 64-Lead LFCSP Pin Configuration (AD8334)
Table 6. 64-Lead LFCSP Pin Function Description (AD8334)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic INH2 LMD2 COM2X LON2 LOP2 VIP2 VIN2 VPS2 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3 COM3 COM4 INH4 LMD4 COM4X LON4 LOP4 VIP4 VIN4 VPS4 GAIN34 CLMP34 Description CH2 LNA Input CH2 LNA VMID Bypass (AC-Coupled to GND) CH2 LNA Ground Shield CH2 LNA Feedback Output (for RFBK) CH2 LNA Output CH2 VGA Positive Input CH2VGA Negative Input CH2 LNA Supply 5 V CH3 LNA Supply 5 V CH3VGA Negative Input CH3 VGA Positive Input CH3 LNA Positive Output CH3 LNA Feedback Output (for RFBK) CH3 LNA Ground Shield CH3 LNA VMID Bypass (AC-Coupled to GND) CH3 LNA Input CH3 LNA Ground CH4 LNA Ground CH4 LNA Input CH4 LNA VMID Bypass (AC-Coupled to GND) CH4 LNA Ground Shield CH4 LNA Feedback Output (for RFBK) CH4 LNA Positive Output CH4 VGA Positive Input CH4VGA Negative Input CH4 LNA Supply 5 V Gain Control Voltage for CH3 and CH4 Output Clamping Level Input for CH3 and CH4
Rev. E | Page 10 of 40
03199-006
AD8331/AD8332/AD8334
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic HILO VCM4 VCM3 NC COM34 VOH4 VOL4 VPS34 VOL3 VOH3 COM34 NC MODE COM12 VOH2 VOL2 VPS12 VOL1 VOH1 COM12 VCM2 VCM1 EN34 EN12 CLMP12 GAIN12 VPS1 VIN1 VIP1 LOP1 LON1 COM1X LMD1 INH1 COM1 COM2 Description Gain Select for Postamp 0 dB or 12 dB CH4 Common-Mode Voltage--AC Bypass CH3 Common-Mode Voltage--AC Bypass No Connect VGA Ground, CH3 and CH4 CH4 Positive VGA Output CH4 Negative VGA Output VGA Supply 5V CH3 and CH4 CH3 Negative VGA Output CH3 Positive VGA Output VGA ground CH3 and CH4 No Connect Gain Control SLOPE, Logic Input, 0 = Positive VGA Ground CH1 and CH2 CH2 Positive VGA Output CH2 Negative VGA Output CH2 VGA Supply 5 V CH1 and CH2 CH1 Negative VGA Output CH1 Positive VGA Output VGA Ground CH1 and CH2 CH2 Common-Mode Voltage--AC Bypass CH1 Common-Mode Voltage--AC Bypass Shared LNA/VGA Enable, CH3 and CH4 Shared LNA/VGA Enable, CH1 and CH2 Output Clamping Level Input, CH1 and CH2 Gain Control Voltage CH1 and CH2 CH1 LNA Supply 5 V CH1 VGA Negative Input CH1 VGA Positive Input CH1 LNA Positive Output CH1 LNA Feedback Output (for RFBK) CH1 LNA Ground Shield CH1 LNA VMID Bypass (AC-Coupled to GND) CH1 LNA Input CH1 LNA Ground CH2 LNA Ground
Rev. E | Page 11 of 40
AD8331/AD8332/AD8334 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, VS = 5 V, RL = 500 , RS = RIN = 50 , RFB = 280 , CSH = 22 pF, f = 10 MHz, RCLMP = , CL = 1 pF, VCM pin floating, -4.5 dB to +43.5 dB gain (HILO = LO), and differential output voltage, unless otherwise specified.
60 50 HILO = HI
PERCENT OF UNITS (%)
50
SAMPLE SIZE = 80 UNITS VGAIN = 0.5V
40
40
GAIN (dB)
30 20 10 HILO = LO
03199-007
30
20
10
03199-010
0 -10
ASCENDING GAIN MODE DESCENDING GAIN MODE (WHERE AVAILABLE) 0 0.2 0.4 0.6 VGAIN (V) 0.8 1.0 1.1
0 -0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
GAIN ERROR (dB)
Figure 7. Gain vs. VGAIN and MODE (MODE Available on AC Package)
2.0 1.5 1.0
GAIN ERROR (dB)
Figure 10. Gain Error Histogram
25 20 15
SAMPLE SIZE = 50 UNITS VGAIN = 0.2V
-40C
+25C
PERCENT OF UNITS (%)
10 5 0 25 20 15 10 VGAIN = 0.7V
0.5 0 -0.5 -1.0 -1.5 -2.0
+85C
03199-008
5
-0.17 -0.15 -0.13 -0.11 -0.09 -0.07 -0.05 -0.03 -0.01 0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19 0.21
0
0
0.2
0.4
0.6 VGAIN (V)
0.8
1.0
1.1
CHANNEL TO CHANNEL GAIN MATCH (dB)
Figure 8. Absolute Gain Error vs. VGAIN at Three Temperatures
2.0 1.5 1.0
GAIN ERROR (dB)
Figure 11. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V
50 40 30
GAIN (dB)
VGAIN = 1V VGAIN = 0.8V VGAIN = 0.6V VGAIN = 0.4V VGAIN = 0.2V
0.5 1MHz 0 -0.5 -1.0 -1.5 -2.0 10MHz 30MHz
20 10 0
50MHz
03199-009
70MHz 0 0.2 0.4 0.6 VGAIN (V) 0.8 1.0 1.1
-20 100k
1M
10M FREQUENCY (Hz)
100M
500M
Figure 9. Absolute Gain Error vs. VGAIN at Various Frequencies
Figure 12. Frequency Response for Various Values of VGAIN
Rev. E | Page 12 of 40
03199-012
-10
VGAIN = 0V
03199-011
AD8331/AD8332/AD8334
60 50 40
GAIN (dB)
VGAIN = 1V VGAIN = 0.8V VGAIN = 0.6V VGAIN = 0.4V VGAIN = 0.2V
0 VOUT = 1V p-p -20 VGAIN = 1.0V
CROSSTALK (dB)
-40
VGAIN = 0.7V VGAIN = 0.4V
AD8332 AD8334
30 20 10
-60
-80
VGAIN = 0V
03199-013
-10 100k
1M
10M FREQUENCY (Hz)
100M
500M
-120 100k
1M
10M FREQUENCY (Hz)
100M
Figure 13. Frequency Response for Various Values of VGAIN, HILO = HI
30 VGAIN = 0.5V 20 RIN = RS = 75 RIN = RS = 50 50 45 40
GROUP DELAY (ns)
Figure 16. Channel-to-Channel Crosstalk vs. Frequency for Various Values of VGAIN
10
GAIN (dB)
35 30 25 20 15 10 1F COUPLING
RIN = RS = 100 RIN = RS = 200 RIN = RS = 500 RIN = RS = 1k
0.1F COUPLING
0
-10
-20
03199-014
5 0 100k 1M 10M FREQUENCY (Hz)
-30 100k
1M
10M FREQUENCY (Hz)
100M
500M
100M
Figure 14. Frequency Response for Various Matched Source Impedances
30 VGAIN = 0.5V RFB = 20
Figure 17. Group Delay vs. Frequency for Two Values of AC Coupling
20 10 0 -10 -20 20 10 0
HI GAIN
T = +85C T = +25C T = -40C
10
GAIN (dB)
0
OFFSET VOLTAGE (mV)
LO GAIN
-10
-20
03199-015
-30 100k
1M
10M FREQUENCY (Hz)
100M
500M
-20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
VGAIN (V)
Figure 15. Frequency Response, Unterminated LNA, RS = 50
Figure 18. Representative Differential Output Offset Voltage vs. VGAIN at Three Temperatures
Rev. E | Page 13 of 40
03199-018
-10
T = +85C T = +25C T = -40C
03199-017
03199-016
0
-100
AD8331/AD8332/AD8334
50j 25j
SAMPLE SIZE = 100 0.2V < VGAIN < 0.7V
35 30 25
100j RIN = 50, RFB = 270
RIN = 6k, RFB = 0 17
f = 100kHz
% TOTAL
20 15 10 5 0
RIN = 75, RFB = 412
03199-019
RIN = 100, RFB = 549 -25j -50j
49.6
49.7
49.8
49.9
50.0
50.1
50.2
50.3
50.4
50.5
RIN = 200, RFB = 1.1k
-100j
03199-022
GAIN SCALING FACTOR
Figure 19. Gain Scaling Factor Histogram
100
20 15
Figure 22. Smith Chart, S11 vs. Frequency, 0.1 MHz to 200 MHz for Various Values of RFB
VIN = 10mV p-p RIN = 50
SINGLE ENDED, PIN VOH OR VOL RL =
RIN = 100
OUTPUT IMPEDANCE ()
10
GAIN (dB)
10 RIN = 200 5 RIN = 500 0 RIN = 1k -5 -10 RIN = 75 -15 100k 1M 10M FREQUENCY (Hz) 100M
1
03199-020
0.1 100k
1M
10M FREQUENCY (Hz)
100M
500M
Figure 20. Output Impedance vs. Frequency
10k RFB = , CSH = 0pF
INPUT IMPEDANCE ()
Figure 23. LNA Frequency Response, Single Ended, for Various Values of RIN
20 15 10
RFB = 6.65k, CSH = 0pF RFB = 3.01k, CSH = 0pF 1k
GAIN (dB)
RFB =
5 0 -5
RFB = 1.1k, CSH = 1.2pF 100 RFB = 549, CSH = 8.2pF
RFB = 412, CSH = 12pF
10 100k
03199-021
1M
10M FREQUENCY (Hz)
100M
-15 100k
1M
10M FREQUENCY (Hz)
100M
500M
Figure 21. LNA Input Impedance vs. Frequency for Various Values of RFB and CSH
Figure 24. Frequency Response for Unterminated LNA, Single Ended
Rev. E | Page 14 of 40
03199-024
RFB = 270, CSH = 22pF
-10
03199-023
AD8331/AD8332/AD8334
500 1.00
f = 10MHz
OUTPUT REFERRED NOISE (nV/ Hz)
400
RS = 0, RFB = , 0.95 VGAIN = 1V, f = 10MHz 0.90
INPUT NOISE (nV/ Hz)
0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 -50 -30 -10 10 30 50 70 90
03199-028
300 LO GAIN HI GAIN 200
AD8332 AD8334 AD8331
100
03199-025
0
0
0.2
0.4 VGAIN (V)
0.6
0.8
1.0
TEMPERATURE (C)
Figure 25. Output-Referred Noise vs. VGAIN
2.5 RS = 0, RFB = , VGAIN = 1V, HILO = LO OR HI
Figure 28. Short-Circuit, Input-Referred Noise vs. Temperature
10
f = 5MHz, RFB = , VGAIN = 1V
2.0
INPUT NOISE (nV/ Hz)
1.5
INPUT NOISE (nV/ Hz)
1
1.0
03199-026
RS THERMAL NOISE ALONE
03199-029
0.5 100k
1M
10M FREQUENCY (Hz)
100M
0.1
1
10
100
1k
Figure 26. Short-Circuit, Input-Referred Noise vs. Frequency
100 7
SOURCE RESISTANCE ()
Figure 29. Input-Referred Noise vs. RS
RS = 0, RFB = , HILO = LO OR HI, f = 10MHz
INCLUDES NOISE OF VGA 6
INPUT NOISE (nV/ Hz)
10
NOISE FIGURE (dB)
5 4 3 2 1
RIN = 50 RIN = 75 RIN = 100 RIN = 200 RFB =
1
03199-027
0.1
0
0.2
0.4 VGAIN (V)
0.6
0.8
1.0
SIMULATION 0 50 100 SOURCE RESISTANCE ()
1k
Figure 27. Short-Circuit, Input-Referred Noise vs. VGAIN
Figure 30. Noise Figure vs. RS for Various Values of RIN
Rev. E | Page 15 of 40
03199-030
AD8331/AD8332/AD8334
35 30 25 HILO = HI, RIN = 50 20 15 HILO = LO, RFB = 10 HILO = HI, RIN =
03199-031
PREAMP LIMITED
f = 10MHz, RS = 50
-30 f = 10MHz, VOUT = 1V p-p -40
HARMONIC DISTORTION (dBc)
HILO = LO, RIN = 50
NOISE FIGURE (dB)
-50 HILO = HI, HD2 -60
HILO = LO, HD2
-70 HILO = HI, HD3 -80
03199-034
HILO = LO, HD3
5 0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
-90
0
200
400
600
800
1000 1200 1400 1600 1800 2000
VGAIN (V)
RLOAD ()
Figure 31. Noise Figure vs. VGAIN
30 f = 10MHz, RS = 50 25 HILO = HI, RIN = 50 HILO = HI, RFB = -40
Figure 34. Harmonic Distortion vs. RLOAD
f = 10MHz, VOUT = 1V p-p
HARMONIC DISTORTION (dBc)
-50 HILO = LO, HD2 HILO = LO, HD3 -60
NOISE FIGURE (dB)
20
15
-70
HILO = HI, HD2 HILO = HI, HD3
10 HILO = LO, RIN = 50 5
03199-032
0 10
15
20
25
30
35
40
45
50
55
60
-90
0
10
20
30
40
50
GAIN (dB)
CLOAD (pF)
Figure 32. Noise Figure vs. Gain
-20 0 -10 G = 30dB, VOUT = 1V p-p
Figure 35. Harmonic Distortion vs. CLOAD
f = 10MHz, GAIN = 30dB
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
-20 -30 -40 -50 -60 -70 -80 -90 1M HILO = HI, HD2 HILO = HI, HD3
03199-033
-40 HILO = LO, HD3 HILO = LO, HD2
HILO = LO, HD2 HILO = LO, HD3
-60
HILO = HI, HD2 -80
HILO = HI, HD3
-100
0
1
2 VOUT (V p-p)
3
4
10M FREQUENCY (Hz)
100
Figure 36. Harmonic Distortion vs. Differential Output Voltage
Figure 33. Harmonic Distortion vs. Frequency
Rev. E | Page 16 of 40
03199-036
03199-035
HILO = LO, RFB =
-80
AD8331/AD8332/AD8334
0 VOUT = 1V p-p -20 -20 INPUT RANGE LIMITED WHEN HILO = LO HILO = LO, HD2 -60 0 -10 VOUT = 1V p-p COMPOSITE (f1 + f2) G = 30dB
DISTORTION (dBc)
-40
HILO = LO, HD3
-30
IMD3 (dBc)
HILO = LO -40 -50 -60
-80 HILO = HI, HD3 HILO = HI, HD2 -120 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0
03199-037
-70
03199-040
-100
-80 HILO = HI -90 1M 10M FREQUENCY (Hz)
100M
Figure 37. Harmonic Distortion vs. VGAIN, f = 1 MHz
0 VOUT = 1V p-p -20 INPUT RANGE LIMITED WHEN HILO = LO HILO = LO, HD2 HILO = LO, HD3 35 40
Figure 40. IMD3 vs. Frequency
10MHz HILO = HI
1MHz HILO = LO 30
DISTORTION (dBc)
OUTPUT IP3 (dBm)
-40
10MHz HILO = LO 25 1MHz HILO = HI 20 15 10
-60
-80 HILO = HI, HD3 -100
03199-038
HILO = HI, HD2
VOUT = 1V p-p COMPOSITE (f1 + f2) 0 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0
-120
0
0.1
0.2
0.3
0.4
0.5 VGAIN (V)
0.6
0.7
0.8
0.9
1.0
Figure 38. Harmonic Distortion vs. VGAIN, f = 10 MHz
10 f = 10MHz 0 HILO = LO
100 90
Figure 41. Output Third-Order Intercept vs. VGAIN
2mV
INPUT POWER (dBm)
-10 HILO = HI -20
10 0
03199-042
-30
03199-039
50mV
10ns
-40
0
0.1
0.2
0.3
0.4
0.5 VGAIN (V)
0.6
0.7
0.8
0.9
1.0
Figure 39. Input 1 dB Compression vs. VGAIN
Figure 42. Small Signal Pulse Response, G = 30 dB, Top: Input, Bottom: Output Voltage, HILO = HI or LO
Rev. E | Page 17 of 40
03199-041
5
AD8331/AD8332/AD8334
5.0
20mV
100 90
4.5 4.0 3.5 HILO = HI HILO = LO
VOUT (V p-p)
10 0
03199-043
3.0 2.5 2.0 1.5 1.0
500mV
10ns
0.5 0 0 5 10 15 20 25 30 35 40 45 50
RCLMP (k)
Figure 43. Large Signal Pulse Response, G = 30 dB, HILO = HI or LO, Top: Input, Bottom: Output Voltage
4 2 G = 30dB CL = 0pF CL = 10pF CL = 22pF CL = 47pF G = 40dB 3 2 1
Figure 46. Clamp Level vs. RCLMP
RCLMP = 48.1k RCLMP = 16.5k
1
INPUT
VOUT (V)
VOUT (V)
INPUT 0 RCLMP = 7.15k -1 -2 RCLMP = 2.67k
0
-1
03199-044 03199-047
-3 INPUT IS NOT TO SCALE -2 -50 -40 -30 -20 -10 -4 -30
-20
-10
0
10
20
30
40
50
60
70
80
0 TIME (ns)
10
20
30
40
50
TIME (ns)
Figure 47. Clamp Level Pulse Response for 4 Values of RCLMP
200mV
Figure 44. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 50 pF
500mV
100 90
10 0
03199-048
100ns 200mV 400ns
03199-045
Figure 48. LNA Overdrive Recovery, VINH 0.05 V p-p to 1 V p-p Burst, VGAIN = 0.27 V VGA Output Shown
Figure 45. Pin GAIN Transient Response, Top: VGAIN, Bottom: Output Voltage
Rev. E | Page 18 of 40
03199-046
AD8331/AD8332/AD8334
1V
100 90
2V
10 0
03199-049
03199-052
100ns
1V
1ms
Figure 49. VGA Overdrive Recovery, VINH 4 mV p-p to 70 mV p-p Burst, VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
0
Figure 52. Enable Response, Large Signal, Top: VENB, Bottom: VOUT, VINH = 150 mV p-p
B
1V
-10
100 90
VPS1, VGAIN = 0.5V
-20 VPSV, VGAIN = 0.5V -30 -40 -50 VPS1, VGAIN = 0V -60
03199-050
10 0
PSRR (dB)
100ns
-80 100k
1M
10M FREQUENCY (Hz)
100M
Figure 50. VGA Overdrive Recovery, VINH 4 mV p-p to 275 mV p-p Burst, VGAIN = 1 V VGA Output Shown Attenuated by 24 dB
140
Figure 53. PSRR vs. Frequency (No Bypass Capacitor)
2V
QUIESCENT SUPPLY CURRENT (mA)
130 120 110 100 90 80 70 60 50 40 30
VGAIN = 0.5V AD8334
AD8332
03199-051
20 -40
-20
0
20
40
60
80
100
TEMPERATURE (C)
Figure 51. Enable Response, Top: VENB, Bottom: VOUT, VINH = 30 mV p-p
B
Figure 54. Quiescent Supply Current vs. Temperature
Rev. E | Page 19 of 40
03199-054
200mV
1ms
AD8331
03199-053
-70
AD8331/AD8332/AD8334 TEST CIRCUITS
MEASUREMENT CONSIDERATIONS
Figure 55 through Figure 68 show typical measurement configurations and proper interface values for measurements with 50 conditions. Short-circuit input noise measurements are made using Figure 62. The input-referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels because a 50 load is driven directly. The generator is removed when noise measurements are made.
NETWORK ANALYZER
OUT
50
50
IN
18nF 270 FERRITE BEAD 120nH 22pF 0.1F 237 28 DUT 237 0.1F
03199-055
0.1F
INH LMD
0.1F
1:1
28
Figure 55. Gain and Bandwidth Measurements
NETWORK ANALYZER
OUT
50
50
IN
18nF 10k FERRITE BEAD 10k 120nH 22pF 0.1F 237 28 DUT 237 0.1F
03199-056
0.1F
INH LMD
0.1F
1:1
28
Figure 56. Frequency Response for Various Matched Source Impedances
NETWORK ANALYZER
OUT
50
50
IN
FERRITE BEAD 120nH 22pF
0.1F
INH LMD
0.1F DUT
237 28 1:1 237
0.1F
0.1F
03199-057
28
Figure 57. Frequency Response for Unterminated LNA, RS = 50
Rev. E | Page 20 of 40
AD8331/AD8332/AD8334
NETWORK ANALYZER
OUT
50
50
IN
18nF 10k FERRITE BEAD 120nH 22pF 0.1F 0.1F AND 10F 0.1F AND 10F INH LMD LNA 0.1F AND 10F VGA 237
03199-058
237 28 1:1
28
Figure 58. Group Delay vs. Frequency for Two Values of AC Coupling
NETWORK ANALYZER FERRITE BEAD 120nH 22pF
18nF 270 237 28 DUT 237 0.1F 28
03199-059
50
OUT
0.1F
INH LMD
0.1F
1:1
50
0.1F
Figure 59. LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) Formats
NETWORK ANALYZER
OUT
50
50
IN 0.1F
FERRITE BEAD 120nH 22pF
0.1F
0.1F INH LMD LNA 0.1F
0.1F VGA
237 28 1:1 237
0.1F
0.1F
03199-060
03199-061
28
Figure 60. Frequency Response for Unterminated LNA, Single Ended
NETWORK ANALYZER 18nF 270 FERRITE BEAD 120nH 22pF 0.1F 0.1F DUT 237 0.1F 28 237 28 1:1 IN 50
0.1F
INH LMD
Figure 61. Short-Circuit, Input-Referred Noise
Rev. E | Page 21 of 40
AD8331/AD8332/AD8334
SPECTRUM ANALYZER A FERRITE BEAD 0.1F 120nH 1 22pF 0.1F GAIN INH LMD 0.1F
03199-062
B IN 50
49.9 50
0.1F
1:1
SIGNAL GENERATOR TO MEASURE GAIN DISCONNECT FOR NOISE MEASUREMENT
Figure 62. Noise Figure
18nF
SPECTRUM ANALYZER 270 IN 50
0.1F -6dB LPF 50 SIGNAL GENERATOR 22pF 0.1F
AD8332
INH LMD
0.1F 1k 28 1:1
-6dB
1k 0.1F
28
03199-063
Figure 63. Harmonic Distortion vs. Load Resistance
SPECTRUM ANALYZER 18nF 270 IN 50
0.1F -6dB LPF 50 SIGNAL GENERATOR 22pF 0.1F
AD8332
INH LMD
0.1F
237 28 237 1:1
-6dB
0.1F
28
03199-064
Figure 64. Harmonic Distortion vs. Load Capacitance
+22dB -6dB FERRITE BEAD 120nH +22dB -6dB COMBINER -6dB 50 22pF 0.1F 18nF 270 0.1F INH LMD DUT 0.1F 0.1F 237 28 237 28 1:1 -6dB
SPECTRUM ANALYZER INPUT 50
50
Figure 65. IMD3 vs. Frequency
Rev. E | Page 22 of 40
03199-065
SIGNAL GENERATORS
AD8331/AD8332/AD8334
OSCILLOSCOPE FERRITE BEAD 120nH 0.1F 50 22pF 0.1F 18nF 270 INH LMD DUT 0.1F 0.1F 237 28 237 28 1:1 50 IN
Figure 66. Pulse Response Measurements
OSCILLOSCOPE FERRITE BEAD 120nH 0.1F 18nF 270 INH DUT 0.1F 255 DIFF PROBE CH1 CH2
22pF LMD 50 RF 0.1F SIGNAL GENERATOR
0.1F 255 TO PIN GAIN OR ENxx 9.5dB
Figure 67. GAIN and Enable Transient Response
NETWORK ANALYZER
OUT 50
50
IN
FERRITE BEAD 120nH 0.1F 22pF 50 RF SIGNAL GENERATOR
18nF 270 INH LMD 0.1F
TO POWER PIN(S) 0.1F DUT 255 DIFF PROBE PROBE POWER
0.1F 255
03199-068
Figure 68. PSRR vs. Frequency
Rev. E | Page 23 of 40
03199-067
50 PULSE GENERATOR
03199-066
AD8331/AD8332/AD8334 THEORY OF OPERATION
OVERVIEW
The following discussion applies to all part numbers. Figure 69, Figure 70, and Figure 71 are functional block diagrams of the AD8331, AD8332, and AD8334, respectively.
LON LOP VIP VIN VCM VMID INH LMD + LNA - LNA BIAS - + ATTENUATOR -48dB HILO 3.5dB/ 15.5dB VOH 21dB PA VOL GAIN INT
LMD2 LNA 2 INH2 LON2 LOP2 VIP2 VIN2 MODE VIN3 VIP3 LOP3 LON3 INH3 LNA 3 LMD3 - ATTENUATOR -48dB + VGA BIAS AND INTERPOLATOR + ATTENUATOR -48dB - 21dB VOH3
PA3
LON1 LOP1 VIP1 VIN1 EN12 INH1 LNA 1 LMD1 LNA BIAS - ATTENUATOR -48dB + VGA BIAS AND INTERPOLATOR + ATTENUATOR -48dB -
VCM1
VMID1
CLAMP
CLMP12 VOH1
21dB
PA1
VOL1 GAIN INT GAIN12 HILO 21dB VOL2
PA2
VOH2
VGA BIAS AND INTERPOLATOR
CLAMP
RCLMP MODE
GAIN UP/ DOWN
VMID2 VMID3
VCM2 VCM3
ENBL
ENBV
GAIN
03199-069
AD8331
VOL3 GAIN INT GAIN34 VOL4
PA4
Figure 69. AD8331 Functional Block Diagram
LON1 LOP1 VIP1 VIN1
VCM1
HILO 3.5dB/ 15.5dB VOH1
PA1
LNA BIAS LMD4 LNA 4 INH4
21dB
VOH4
+19dB INH1 LNA 1 LMD1 BIAS (VMID) LMD2 LNA 2 INH2 - ATTENUATOR -48dB + VGA BIAS AND INTERPOLATOR + ATTENUATOR -48dB -
VMID
AD8334
CLAMP34 VMID4
CLMP34
21dB
VOL1
LON4 LOP4 VIP4 VIN4 EN34 VCM4
GAIN INT
GAIN VOL2
PA2
Figure 71. AD8334 Functional Block Diagram
21dB
VOH2 VMID CLAMP RCLMP
03199-070
AD8332
LON2 LOP2 VIP2 VIN2 ENB
VCM2
Each channel contains an LNA that provides user-adjustable input impedance termination, a differential X-AMP VGA, and a programmable gain postamplifier with adjustable output voltage limiting. Figure 72 shows a simplified block diagram with external components.
HILO LON VIN SIGNAL PATH PRE-AMPLIFIER 19dB + LNA - 3.5dB/15.5dB VOH 21dB POSTAMP VOL
Figure 70. AD8332 Functional Block Diagram
INH LMD
48dB ATTENUATOR VMID
LOP BIAS (VMID)
VIP
VCM GAIN INTERFACE CLAMP RCLMP
03199-072
BIAS AND INTERPOLATOR
GAIN
Figure 72. Simplified Block Diagram
Rev. E | Page 24 of 40
03199-071
AD8331/AD8332/AD8334
The linear-in-dB gain-control interface is trimmed for slope and absolute accuracy. The gain range is 48 dB, extending from -4.5 dB to +43.5 dB in HI gain and +7.5 dB to +55.5 dB in LO gain mode. The slope of the gain control interface is 50 dB/V, and the gain control range is 40 mV to 1 V. Equation 1 and Equation 2 are the expressions for gain. GAIN (dB) = 50 (dB/V) x VGAIN - 6.5 dB, (HILO = LO) or GAIN (dB) = 50 (dB/V) x VGAIN + 5.5 dB, (HILO = LO) The ideal gain characteristics are shown in Figure 73.
60 50
LOW NOISE AMPLIFIER (LNA)
Good noise performance relies on a proprietary ultralow noise preamplifier at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input matching. A simplified schematic of the LNA is shown in Figure 74. INH is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of 3.25 V and centers the output common-mode levels at 2.5 V. A Capacitor CLMD of the same value as the Input Coupling Capacitor CINH is connected from the LMD pin to ground.
CFB LOP VPOS RFB LON
(1)
(2)
40
GAIN (dB)
HILO = HI
30 20 10 0 -10
I0 CINH
HILO = LO
I0
INH CSH
Q1
Q2
LMD CLMD
RS
03199-073
0
0.2
0.4
0.6 VGAIN (V)
0.8
1.0
1.1
Figure 74. Simplified LNA Schematic
Figure 73. Ideal Gain Control Characteristics
The gain slope is negative with the MODE pulled high (where available): GAIN (dB) = -50 (dB/V) x VGAIN + 45.5 dB, (HILO = LO) or GAIN (dB) = -50 (dB/V) x VGAIN + 57.5 dB, (HILO = HI) (4) (3)
The LNA supports differential output voltages as high as 5 V p-p with positive and negative excursions of 1.25 V, about a common-mode voltage of 2.5 V. Because the differential gain magnitude is 9, the maximum input signal before saturation is 275 mV or +550 mV p-p. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred voltage noise of 0.74 nV/Hz. This is achieved with a current consumption of only 11 mA per channel (55 mW). On-chip resistor matching results in precise single-ended gains of 4.5x (9x differential), critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion.
The LNA converts a single-ended input to a differential output with a voltage gain of 19 dB. If only one output is used, the gain is 13 dB. The inverting output is used for active input impedance termination. Each of the LNA outputs is capacitively coupled to a VGA input. The VGA consists of an attenuator with a range of 48 dB followed by an amplifier with 21 dB of gain for a net gain range of -27 dB to +21 dB. The X-AMP gain-interpolation technique results in low gain error and uniform bandwidth, and differential signal paths minimize distortion. The final stage is a logic programmable amplifier with gains of 3.5 dB or 15.5 dB. The LO and HI gain modes are optimized for 12-bit and 10-bit ADC applications, in terms of output-referred noise and absolute gain range. Output voltage limiting can be programmed by the user.
Rev. E | Page 25 of 40
03199-074
ASCENDING GAIN MODE DESCENDING GAIN MODE (WHERE AVAILABLE)
I0
I0
AD8331/AD8332/AD8334
Active Impedance Matching
The LNA supports active impedance matching through an external shunt feedback resistor from Pin LON to Pin INH. The input resistance, RIN, is given by Equation 5, where A is the singleended gain of 4.5, and 6 k is the unterminated input impedance.
RIN 6 k x RFB R = FB 6 k = 1+ A 33 k + RFB
RS VIN + - RESISTIVE TERMINATION RS VIN + - RIN RS UNTERMINATED RIN
VOUT
(5)
VOUT
CFB is needed in series with RFB because the dc levels at Pin LON and Pin INH are unequal. Expressions for choosing RFB in terms of RIN and for choosing CFB are found in the Applications section. CSH and the ferrite bead enhance stability at higher frequencies where the loop gain is diminished and prevent peaking. Frequency response plots of the LNA are shown in Figure 23 and Figure 24. The bandwidth is approximately 130 MHz for matched input impedances of 50 to 200 and declines at higher source impedances. The unterminated bandwidth (when RFB = ) is approximately 80 MHz. Each output can drive external loads as low as 100 in addition to the 100 input impedance of the VGA (200 differential). Capacitive loading up to 10 pF is permissible. All loads should be ac-coupled. Typically, Pin LOP output is used as a singleended driver for auxiliary circuits, such as those used for Doppler ultrasound imaging, and Pin LON drives RFB. Alternatively, a differential external circuit can be driven from the two outputs in addition to the active feedback termination. In both cases, important stability considerations discussed in the Applications section should be carefully observed. The impedance at each LNA output is 5 . A 0.4 dB reduction in open-circuit gain results when driving the VGA, and 0.8 dB with an additional 100 load at the output. The differential gain of the LNA is 6 dB higher. If the load is less than 200 on either side, a compensating load is recommended on the opposite output.
7
ACTIVE IMPEDANCE MATCH RFB R RS VIN + - RFB 1 + 4.5
03199-075
IN
VOUT
RIN =
Figure 75. Input Configurations
INCLUDES NOISE OF VGA 6 5 4 3 ACTIVE IMPEDANCE MATCH 2 1 SIMULATION 0 50 100 UNTERMINATED 1k RS () RESISTIVE TERMINATION (RS = RIN)
NOISE FIGURE (dB)
Figure 76. Noise Figure vs. RS for Resistive, Active Matched and Unterminated Inputs
7 INCLUDES NOISE OF VGA 6 5 4 3 2 1 SIMULATION 0 50 100 RS ()
LNA Noise
The input-referred voltage noise sets an important limit on system performance. The short-circuit input voltage noise of the LNA is 0.74 nV/Hz or 0.82 nV/Hz (at maximum gain), including the VGA noise. The open-circuit current noise is 2.5 pA/Hz. These measurements, taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations in Figure 75. Figure 76 and Figure 77 are simulations extracted from these results, and the 4.1 dB NF measurement with the input actively matched to a 50 source. Unterminated (RFB = ) operation exhibits the lowest equivalent input noise and noise figure. Figure 76 shows the noise figure vs. source resistance, rising at low RS, where the LNA voltage noise is large compared to the source noise, and again at high RS due to current noise. The VGA's input-referred voltage noise of 2.7 nV/Hz is included in all of the curves.
NOISE FIGURE (dB)
RIN = 50 RIN = 75 RIN = 100 RIN = 200 RFB =
03199-077
1k
Figure 77. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched
Rev. E | Page 26 of 40
03199-076
AD8331/AD8332/AD8334
The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA's input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 76 shows their relative noise figure (NF) performance. In this graph, the input impedance was swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 are 7.1 dB, 4.1 dB, and 2.5 dB, respectively, for the resistive, active, and unterminated configurations. The noise figures for 200 are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. Figure 77 is a plot of the NF vs. RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 19 dB and noise spectral density of 1.0 nV/Hz, combined with a VGA with 3.75 nV/Hz, yields a noise figure degradation of approximately 1.5 dB (for most input impedances), significantly worse than the AD8332 performance. The equivalent input noise of the LNA is the same for singleended and differential output applications. The LNA noise figure improves to 3.5 dB at 50 without VGA noise, but this is exclusive of noise contributions from other external circuits connected to LOP. A series output resistor is usually recommended for stability purposes when driving external circuits on a separate board (see the Applications section). In low noise applications, a ferrite bead is even more desirable.
X-AMP VGA
The input of the VGA is a differential R-2R ladder attenuator network with 6 dB steps per stage and a net input impedance of 200 differential. The ladder is driven by a fully differential input signal from the LNA and is not intended for single-ended operation. LNA outputs are ac-coupled to reduce offset and isolate their common-mode voltage. The VGA inputs are biased through the ladder's center tap connection to VCM, which is typically set to 2.5 V and is bypassed externally to provide a clean ac ground. The signal level at successive stages in the input attenuator falls from 0 dB to -48 dB in 6 dB steps. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to -48 dB. This circuit technique results in excellent, linear-in-dB gain law conformance and low distortion levels and deviates 0.2 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a gain-of-12 feedback amplifier that completes the VGA. Its bandwidth is 150 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across gain setting (see Figure 12 and Figure 13).
Gain Control
Position along the VGA attenuator is controlled by a singleended analog control voltage, VGAIN, with an input range of 40 mV to 1.0 V. The gain control scaling is trimmed to a slope of 50 dB/V (20 mV/dB). Values of VGAIN beyond the control range saturate to minimum or maximum gain values. Both channels of the AD8332 are controlled from a single gain interface to preserve matching. Gain can be calculated using Equation 1 and Equation 2. Gain accuracy is very good because both the scaling factor and absolute gain are factory trimmed. The overall accuracy relative to the theoretical gain expression is 1 dB for variations in temperature, process, supply voltage, interpolator gain ripple, trim errors, and tester limits. The gain error relative to a best-fit line for a given set of conditions is typically 0.2 dB. Gain matching between channels is better than 0.1 dB (Figure 11 shows gain errors in the center of the control range). When VGAIN < 0.1 or > 0.95, gain errors are slightly greater.
VARIABLE GAIN AMPLIFIER
The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 2.7 nV/Hz and excellent gain linearity. A simplified block diagram is shown in Figure 78.
GAIN GAIN INTERPOLATOR (BOTH CHANNELS) + gm VIP 6dB R VIN 48dB 2R POSTAMP
- POSTAMP
Figure 78. Simplified VGA Schematic
Rev. E | Page 27 of 40
03199-078
AD8331/AD8332/AD8334
The gain slope can be inverted, as shown in Figure 73 (available in most versions). The gain drops with a slope of -50 dB/V across the gain control range from maximum to minimum gain. This slope is useful in applications, such as automatic gain control, where the control voltage is proportional to the measured output signal amplitude. The inverse gain mode is selected by setting the MODE pin HI. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. signal. A transformer can be used with single-ended applications when low noise is desired. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and usually only evident when a large signal is present. Its effect is observable only in LO gain mode, where the noise floor is substantially lower. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN input. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth.
VGA Noise
In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. While the input-referred noise of the LNA limits the minimum resolvable input signal, the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC. Output and input-referred noise as a function of VGAIN are plotted in Figure 25 and Figure 27 for the short-circuited input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is flat over most of the gain range, because it is dominated by the fixed output-referred noise of the VGA. Values are 48 nV/Hz in LO gain mode and 178 nV/Hz in HI gain mode. At the high end of the gain control range, the noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA becomes very small. At lower gains, the input-referred noise, and thus noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases with it. The contribution of the ADC noise floor has the same dependence as well. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. With its low output-referred noise levels, these devices ideally drive low voltage ADCs. The converter noise floor drops 12 dB for every 2 bits of resolution and drops at lower input full-scale voltages and higher sampling rates. ADC quantization noise is discussed in the Applications section. The preceding noise performance discussion applies to a differential VGA output signal. Although the LNA noise performance is the same in single-ended and differential applications, the VGA performance is not. The noise of the VGA is significantly higher in single-ended usage, because the contribution of its bias noise is designed to cancel in the differential
Common-Mode Biasing
An internal bias network connected to a midsupply voltage establishes common-mode voltages in the VGA and postamp. An externally bypassed buffer maintains the voltage. The bypass capacitors form an important ac ground connection, because the VCM network makes a number of important connections internally, including the center tap of the VGA's differential input attenuator, the feedback network of the VGA's fixed gain amplifier, and the feedback network of the postamplifier in both gain settings. For best results, use a 1 nF and a 0.1 F capacitor in parallel, with the 1 nF nearest to the VCM pin. Separate VCM pins are provided for each channel. For dc-coupling to a 3 V ADC, the output common-mode voltage is adjusted to 1.5 V by biasing the VCM pin.
POSTAMPLIFIER
The final stage has a selectable gain of 3.5 dB (x1.5) or 15.5 dB (x6), set by the logic pin, HILO. Figure 79 is a simplified block diagram.
+ Gm2 VOH Gm1 F2
VCM
F1
Gm2 - Gm1
03199-079
VOL
Figure 79. Postamplifier Block Diagram
Separate feedback attenuators implement the two gain settings. These are selected in conjunction with an appropriately scaled input stage to maintain a constant 3 dB bandwidth between the two gain modes (~150 MHz). The slew rate is 1200 V/s in HI gain mode and 300 V/s in LO gain mode. The feedback networks for HI and LO gain modes are factory trimmed to adjust the absolute gains of each channel.
Rev. E | Page 28 of 40
AD8331/AD8332/AD8334
Noise
The topology of the postamplifier provides constant inputreferred noise with the two gain settings and variable output-referred noise. The output-referred noise in HI gain mode increases (with gain) by four. This setting is recommended when driving converters with higher noise floors. The extra gain boosts the output signal levels and noise floor appropriately. When driving circuits with lower input noise floors, the LO gain mode optimizes the output dynamic range. Although the quantization noise floor of an ADC depends on a number of factors, the 48 nV/Hz and 178 nV/Hz levels are well suited to the average requirements of most 12-bit and 10-bit converters, respectively. An additional technique, described in the Applications section, can extend the noise floor even lower for possible use with 14-bit ADCs. Output clamping can be used for ADC input overload protection, if needed, or postamp overload protection when operating from a lower common-mode level, such as 1.5 V. The user should be aware that distortion products increase as output levels approach the clamping levels, and the user should adjust the clamp resistor accordingly. For additional information, see the Applications section. The accuracy of the clamping levels is approximately 5% in LO or HI mode. Figure 80 illustrates the output characteristics for a few values of RCLMP.
5.0 4.5 4.0 8.8k 3.5 3.5k 3.0 2.5 2.0 1.5 1.0 0.5 0 -3 RCLMP = 1.86k 3.5k 8.8k RCLMP =
Output Clamping
Outputs are internally limited to a level of 4.5 V p-p differential when operating at a 2.5 V common-mode voltage. The postamp implements an optional output clamp engaged through a resistor from RCLMP to ground. Table 8 shows a list of recommended resistor values.
VOH, VOL (V)
-2
-1
0 VINH (V)
1
2
3
Figure 80. Output Clamping Characteristics
Rev. E | Page 29 of 40
03199-080
RCLMP =
AD8331/AD8332/AD8334 APPLICATIONS
LNA--EXTERNAL COMPONENTS
The LMD pin (connected to the bias circuitry) must be bypassed to ground and signal sourced to the INH pin capacitively coupled using 2.2 nF to 0.1 F capacitors (see Figure 81).
5V 1 2 3 4 5 6 7 0.1F 1nF 8 9 1nF 10 11 0.1F 1nF 12 13 14 CLMD 0.1F LMD2 INH2 VPS2 LON2 LOP2 COM2 VIP2 VIN2 VCM2 GAIN RCLMP VOH2 VOL2 COMM LMD1 INH1 VPS1 LON1 LOP1 COM1 VIP1 VIN1 VCM1 HILO ENB VOH1 VOL1 VPSV 28 27 26 25 24 23 22 0.1F 21 20 19 18 17 16 15 1nF *SEE TEXT 1nF 5V 5V 0.1F CFB* RFB* 1nF LNA OUT CSH* 5V 0.1F FB LNA SOURCE 0.1F
The unterminated input impedance of the LNA is 6 k. The user can synthesize any LNA input resistance between 50 and 6 k. RFB is calculated according to Equation 6 or selected from Table 7.
RFB = 33 k x (RIN ) 6 k - (RIN )
(6)
Table 7. LNA External Component Values for Common Source Impedances
RIN () 50 75 100 200 500 6k RFB (Nearest STD 1% Value, ) 280 412 562 1.13 k 3.01 k CSH (pF) 22 12 8 1.2 None None
VGAIN
* *
VGA OUT VGA OUT 5V 0.1F
03199-081
When active input termination is used, a decoupling capacitor (CFB) is required to isolate the input and output bias voltages of the LNA. The shunt input capacitor, CSH, reduces gain peaking at higher frequencies where the active termination match is lost due to the gain roll-off of the LNA at high frequencies. The value of CSH diminishes as RIN increases to 500 , at which point no capacitor is required. Suggested values for CSH for 50 RIN 200 are shown in Table 7. When a long trace to Pin INH is unavoidable, or if both LNA outputs drive external circuits, a small ferrite bead (FB) in series with Pin INH preserves circuit stability with negligible effect on noise. The bead shown is 75 at 100 MHz (Murata BLM21 or equivalent). Other values can prove useful. Figure 82 shows the interconnection details of the LNA output. Capacitive coupling between the LNA outputs and the VGA inputs is required because of the differences in their dc levels and the need to eliminate the offset of the LNA. Capacitor values of 0.1 F are recommended. There is 0.4 dB loss in gain between the LNA output and the VGA input due to the 5 output resistance. Additional loading at the LOP and LON outputs affect LNA gain.
Figure 81. Basic Connections for a Typical Channel (AD8332 Shown)
RFB LNA DECOUPLING RESISTOR TO EXT CIRCUIT
5 LON
VIP
50 100
VCM LNA CSH 5 LOP VIN
100 50
TO EXT CIRCUIT
Figure 82. Interconnections of the LNA and VGA
Both LNA outputs are available for driving external circuits. Pin LOP should be used in those instances when a single-ended LNA output is required. The user should be aware of stray capacitance loading of the LNA outputs, in particular LON. The LNA can drive 100 in parallel with 10 pF. If an LNA output is routed to a remote PC board, it tolerates a load capacitance up to 100 pF with the addition of a 49.9 series resistor or ferrite 75 /100 MHz bead.
Gain Input
The GAIN pin is common to both channels of the AD8332. The input impedance is nominally 10 M and a bypass capacitor from 100 pF to1 nF is recommended.
Rev. E | Page 30 of 40
03199-082
LNA DECOUPLING RESISTOR
AD8331/AD8332/AD8334
Parallel connected devices can be driven by a common voltage source or DAC. Decoupling should take into account any bandwidth considerations of the drive waveform, using the total distributed capacitance. If gain control noise in LO gain mode becomes a factor, maintaining 15 nV/Hz noise at the GAIN pin ensures satisfactory noise performance. Internal noise prevails below 15 nV/Hz at the GAIN pin. Gain control noise is negligible in HI gain mode.
Optional Output Voltage Limiting
The RCLMP pin provides the user with a means to limit the output voltage swing when used with loads that have no provisions for prevention of input overdrive. The peak-to-peak limited voltage is adjusted by a resistor to ground, and Table 8 lists several voltage levels and the corresponding resistor value. Unconnected, the default limiting level is 4.5 V p-p. Note that third harmonic distortion increases as waveform amplitudes approach clipping. For lowest distortion, the clamp level should be set higher than the converter input span. A clamp level of 1.5 V p-p is recommended for a 1 V p-p linear output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a 0.5 V p-p operation. The best solution is determined experimentally. Figure 84 shows third harmonic distortion as a function of the limiting level for a 2 V p-p output signal. A wider limiting level is desirable in HI gain mode.
-20 VGAIN = 0.75V -30
VCM Input
The common-mode voltage of Pin VCM, Pin VOL, and Pin VOH defaults to 2.5 V dc. With output ac-coupled applications, the VCM pin is unterminated; however, it must still be bypassed in close proximity for ac grounding of internal circuitry. The VGA outputs can be dc connected to a differential load, such as an ADC. Common-mode output voltage levels between 1.5 V and 3.5 V can be realized at Pin VOH and Pin VOL by applying the desired voltage at Pin VCM. DC-coupled operation is not recommended when driving loads on a separate PC board. The voltage on the VCM pin is sourced by an internal buffer with an output impedance of 30 and a 2 mA default output current (see Figure 83). If the VCM pin is driven from an external source, its output impedance should be <<30 and its current drive capability should be >>2 mA. If the VCM pins of several devices are connected in parallel, the external buffer should be capable of overcoming their collective output currents. When a common-mode voltage other than 2.5 V is used, a voltage-limiting resistor, RCLMP, is needed to protect against overload.
2mA MAX INTERNAL CIRCUITRY 30 VCM 100pF AC GROUNDING FOR INTERNAL CIRCUITRY RO << 30 NEW VCM
-40
HD3 (dBc)
-50 HILO = LO
-60
-70
HILO = HI
03199-084
-80 1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
CLAMP LIMIT LEVEL (V p-p)
Figure 84. HD3 vs. Clamping Level for 2 V p-p Differential Input
Table 8. Clamp Resistor Values
Clamp Level (V p-p) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.4 Clamp Resistor Value (k) HILO = LO HILO = HI 1.21 2.74 2.21 4.75 4.02 7.5 6.49 11 9.53 16.9 14.7 26.7 23.2 49.9 39.2 100 73.2
0.1F
03199-083
Figure 83. VCM Interface
Logic Inputs--ENB, MODE, and HILO
The input impedance of all enable pins is nominally 25 k and can be pulled up to 5 V (a pull-up resistor is recommended) or driven by any 3 V or 5 V logic families. The enable pin, ENB, powers down the VGA--when pulled low, the VGA output voltages are near ground. Multiple devices can be driven from a common source. Consult Table 3, Table 4, Table 5, and Table 6 for circuit functions controlled by the enable pins. Pin HILO is compatible with 3 V or 5 V CMOS logic families. It is either connected to ground or pulled up to 5 V, depending on the desired gain range and output noise.
Rev. E | Page 31 of 40
AD8331/AD8332/AD8334
Output Decoupling
When driving capacitive loads greater than about 10 pF, or long circuit connections on other boards, an output network of resistors and/or ferrite beads can be useful to ensure stability. These components can be incorporated into a Nyquist filter such as the one shown in Figure 81. In Figure 81, the resistor value is 84.5 . The AD8332-EVAL incorporates 100 in parallel with a 120 nH bead. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. The exact values of these components can be selected empirically. An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and to mitigate charge kickback from the ADC inputs. Any series resistance beyond that required for output stability should be placed on the ADC board. Figure 85 shows a second-order, low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC.
OPTIONAL BACKPLANE 84.5 84.5 0.1F 0.1F 1.5H 158
03199-085
4V p-p DIFF, 48nV/ Hz 187
2V p-p DIFF, 24nV/ Hz
VOH VOL
187
Figure 86. Adjusting the Noise Floor for 14-Bit ADCs
OVERLOAD
These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. Signals larger than 275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 48 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as 2.5 V without triggering the slow-settling ESD input protection diodes. Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited output characteristics found in Figure 49. Recovery is fast in all cases. The graph in Figure 87 summarizes the combinations of input signal and gain that lead to the different types of overload.
POSTAMP OVERLOAD 43.5 15mV X-AMP OVERLOAD 25mV 56.5 POSTAMP OVERLOAD 4mV X-AMP OVERLOAD 25mV
1.5H
158
18pF
ADC
Figure 85. 20 MHz Second-Order, Low-Pass Filter
DRIVING ADCs
The output drive accommodates a wide range of ADCs. The noise floor requirements of the VGA depend on a number of application factors, including bit resolution, sampling rate, fullscale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range can be adjusted by selecting HI or LO gain mode. The relative noise and distortion performance of the two gain modes can be compared in Figure 25 and Figure 31 through Figure 41. The 48 nV/Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC fullscale voltages as high as 4 V p-p. Because distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 36), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 86 has an output full-scale range of 2 V p-p, a gain range of -10.5 dB to +37.5 dB, and an output noise floor of 24 nV/Hz, making it suitable for some 14-bit ADC applications.
03199-086
2:1
374
LPF
AD6644
ADC
41dB 29dB
GAIN (dB)
GAIN (dB)
24.5dB
24.5dB
LNA OVERLOAD
10m
0.1 0.275
1
1m
INPUT AMPLITUDE (V)
10m 0.1 0.275 INPUT AMPLITUDE (V)
1
Figure 87. Overload Gain and Signal Conditions
The previously mentioned clamp interface controls the maximum output swing of the postamp and its overload response. When the clamp feature is not used, the output level defaults to approximately 4.5 V p-p differential centered at 2.5 V common mode. When other common-mode levels are set through the VCM pin, the value of RCLMP should be selected for graceful overload. A value of 8.3 k or less is recommended for 1.5 V or 3.5 V common-mode levels (7.2 k for HI gain mode). This limits the output swing to just above 2 V p-p differential.
Rev. E | Page 32 of 40
03199-087
-4.5 1m
7.5
LNA OVERLOAD
LO GAIN MODE
HI GAIN MODE
AD8331/AD8332/AD8334
OPTIONAL INPUT OVERLOAD PROTECTION
Applications in which high transients are applied to the LNA input can benefit from the use of clamp diodes. A pair of backto-back Schottky diodes can reduce these transients to manageable levels. Figure 88 illustrates how such a diode-protection scheme can be connected.
OPTIONAL SCHOTTKY OVERLOAD CLAMP FB 3 COMM 20 0.1F RSH CSH 2 1 CFB RFB 2 INH ENBL 19
MULTIPLE INPUT MATCHING
Matching of multiple sources with dissimilar impedances can be accomplished as shown in Figure 90. A relay and low supply voltage analog switch can be used to select between multiple sources and their associated feedback resistors. An ADG736 dual SPDT switch is shown in this example; however, multiple switches are also available and users are referred to the Analog Devices Selection Guide for switches and multiplexers.
DISABLING THE LNA
Where accessible, connection of the LNA enable pin to ground powers down the LNA, resulting in a current reduction of about half. In this mode, the LNA input and output pins can be left unconnected; however, the power must be connected to all the supply pins for the disabling circuit to function. Figure 89 illustrates the connections using an AD8331 as an example.
NC 1 LMD COMM 20
3 VPSL 4 LON
BAS40-04
Figure 88. Input Overload Clamping
When selecting overload protection, the important parameters are forward and reverse voltages and trr (or rr). The Infineon BAS40-04 series shown in Figure 88 has a rr of 100 ps and VF of 310 mV at 1 mA. Many variations of these specifications can be found in vendor catalogs.
03199-088
AD8331
NC 2 INH ENBL 19
LAYOUT, GROUNDING, AND BYPASSING
Due to their excellent high frequency characteristics, these devices are sensitive to their PCB environment. Realizing expected performance requires attention to detail critical to good high speed board design. A multilayer board with power and ground planes is recommended with blank areas in the signal layers filled with ground plane. Be certain that the power and ground pins provided for robust power distribution to the device are connected. Decouple the power supply pins with surface-mount capacitors as close as possible to each pin to minimize impedance paths to ground. Decouple the LNA power pins from the VGA supply using ferrite beads. Together with the capacitors, ferrite beads eliminate undesired high frequencies without reducing the headroom. Use a larger value capacitor for every 10 chips to 20 chips to decouple residual low frequency noise. To minimize voltage drops, use a 5 V regulator for the VGA array. Several critical LNA areas require special care. The LON and LOP output traces must be as short as possible before connecting to the coupling capacitors connected to Pin VIN and Pin VIP. RFB must be placed near the LON pin as well. Resistors must be placed as close as possible to the VGA output pins, VOL and VOH, to mitigate loading effects of connecting traces. Values are discussed in the Output Decoupling section. Signal traces must be short and direct to avoid parasitic effects. Wherever there are complementary signals, symmetrical layout should be employed to maintain waveform balance. PCB traces should be kept adjacent when running differential signals over a long distance.
5V
CFB 0.018F 3 VPSL ENBV 18 5V
NC
4
LON
COMM
17
NC
5
LOP
VOL
16
VOUT 6 COML VOH 15
0.1F
7
VIP
VPOS
14
5V
VIN 0.1F
8
VIN
HILO
13
HILO
MODE
9
MODE
RCLMP
12 RCLMP
GAIN
10
GAIN
VCM
11
VCM
03199-089
Figure 89. Disabling the LNA
Rev. E | Page 33 of 40
AD8331/AD8332/AD8334
ADG736
1.13k SELECT RFB 280
18nF 200 INH LMD 50 0.1F LNA
LON 5
Using the EVAL-AD8332/AD9238 evaluation board and a high speed ADC FIFO evaluation kit connected to a laptop, an FFT can be performed on the AD8332. With the on-board clock of 20 MHz, minimal low-pass filtering, and both channels driven with a 1 MHz filtered sine wave, the THD is -75 dB, noise floor is -93 dB, and HD2 is -83 dB.
HIGH DENSITY QUAD LAYOUT
LOP 5
03199-090
AD8332
Figure 90. Accommodating Multiple Sources
ULTRASOUND TGC APPLICATION
The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, because it provides the means for echolocation of reflected ultrasound energy. Figure 91 through Figure 93 are schematics of a dual, fully differential system using the AD8332 and the AD9238, 12-bit high speed ADC with conversion speeds as high as 65 MSPS.
The AD8334 is the ideal solution for applications with limited board space. Figure 94 represents four channels routed to and away from this very compact quad VGA. Note that none of the signal paths crosses and that all four channels are spaced apart to eliminate crosstalk. In this example, all of the components shown are 0402 size; however, the same layout is executable at the expense of slightly more board area. The sketch also assumes that both sides of the printed circuit board are available for components, and that the bypass and power supply decoupling circuitry is located on the wiring side of the board.
Rev. E | Page 34 of 40
AD8331/AD8332/AD8334
S3 EIN2 TP5 C50 0.1F 1 C49 0.1F 2 CFB2 18nF + C46 1F C80 22pF +5VLNA RFB2 274 C41 0.1F C74 1nF 4 JP5 IN2 3 VPS2 VPS1 26 +5VLNA 25
AD8332ARU
LMD2 LMD1 28 C70 0.1F 27 JP6 IN1 C79 22pF TP6 L13 120nH FB C60 0.1F
TP3 (RED) TB1 +5V TP4 (BLACK) TB2 GND
L12 120nH FB +5V
INH2
INH1
S1 EIN1
CFB1 18nF RFB1 274
L7 120nH FB +5VGA
LON2
LON1
L6 120nH FB +5VLNA C51 0.1F C53 0.1F
5
LOP2
LOP1
24
6
COM2
COM1
23
C42 0.1F
C59 0.1F
7
VIP2
VIP1
22
VCM1
8
VIN2
VIN1
21 VCM1
JP13
C48 0.1F
C78 1nF
9
VCM2
VCM1
20 C77 1nF C43 0.1F +5VGA HI GAIN JP10 LO GAIN
TP2 GAIN TP7 GND
10 C83 1nF 11 C69 0.1F R27 100 L11 120nH FB 13 C68 1nF 12
GAIN
HILO
19 +5VGA
R3 (RCLMP)
RCLMP
ENB
18
ENABLE JP16 DISABLE
OPTIONAL 4-POLE LOW-PASS FILTER VIN+B C66 SAT VIN-B L19 SAT C67 L20 SAT SAT L17 SAT
JP8 DC2H C54 0.1F
VOH2
VOH1
17 R24 100 16 L9 120nH FB JP9 C58 0.1F JP17 C56 0.1F OPTIONAL 4-POLE LOW-PASS FILTER L1 SAT L15 SAT C64 SAT L16 SAT VIN+A C65 SAT
VOL2
VOL1
L18 JP12 SAT
C55 0.1F JP7 DC2L
L10 120nH FB
14
COM
VPSV
15
L8 120nF FB
L14 SAT
VIN-A R26 100 +5VGA C45 0.1F R25 100 C85 1nF JP10
03199-091
Figure 91. Schematic, TGC, VGA Section Using an AD8332 and AD9238
Rev. E | Page 35 of 40
AD8331/AD8332/AD8334
VR1 ADP3339AKC-3.3 C44 1F
+ 2 1
L5 120nH FB C31 0.1F L4 120nH FB C30 0.1F L3 120nH FB C29 0.1F L2 120nH FB C1 0.1F C36 0.1F VREF C38 0.1F C34 10F 6.3V R5 33 C2 10F 6.3V
+3.3VAVDD
+5V 3
C22 0.1F +
1 2
C21 1nF
ADCLK
64 63 62 61 60 59 58 57 56 55 54 53
IN OUT GND
AGND VIN+_A VIN-_A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B
AVDD CLK_A SHARED_REF MUX_SELECT PDWN_A OEB_A OTR_A D11_A (MSB) D10_A D9_A
OUT TAB
VIN+_A VIN-_A R12 1.5k C35 0.1F
C61 18pF R4 C18 1.5k C17 1nF C33 0.1F 10F 6.3V + C40 0.1F TP9 C32 + 0.1F C12 10F 6.3V C57 10nF R6 33
3 4 5 6
R11 100 R10 JP2 0 SHARED REF Y N R14 4.7k R15 +3.3VADDIG 0
C52 10nF
7 8 9 10
OTR_A D11_A D10_A D9_A D8_A +3.3VADDIG C23 0.1F D7_A D6_A D5_A D4_A D3_A D2_A D1_A D0_A DNC DNC C13 1nF OTR_B D11_B D10_B D9_B D8_B D7_B D6_B C14 + 0.1F C11 10F 6.3V C25 1nF
C37 0.1F 1.5k C16 1.5k 0.1F R8 33 C15 1nF
12 13 14
AVDD AGND VIN-_B VIN+_B AGND AVDD CLK_B DCS DFS PDWN_B OEB_B DNC DNC D0_B D1_B D2_B DRGND DRVDD D3_B D4_B D5_B
U1 A/D CONVERTER AD9238
C39 10F
11
REFT_B
D8_A DRGND
DRVDD 52 D7_A D6_A D5_A D4_A D3_A D2_A D1_A D0_A DNC DNC DRVDD DRGND OTR_B
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VIN-B VIN+B
C62 18pF R7 33
15 16 17
+3.3VCLK R18 499 R16 5k R19 499
S2 EXT CLOCK
C63 0.1F
C20 0.1F
C19 1nF
18 19
R17 49.9
JP3 R20 4.7k
JP11 R41 4.7k
20 21 22
+3.3VCLK ADCLK C86 0.1F + C47 10F 6.3V EXT 3 JP4 2 1 INT 3 ADCLK U5 74VHC04 4 1 U5 74VHC04 2 DNC DNC R9 0 D0_B D1_B D2_B
23 24 25 26 27 28 29
TP 12
4 1 VDD OE 20MHz 3 OUT GND 2
U6 SG-636PCE
U5 74VHC04 5 6
U5 74VHC04 9 8
TP 13 DATA CLK 3 1 JP1 2
D11_B (MSB) D10_B D9_B D8_B D7_B D6_B
D3_B D4_B D5_B
30 31 32
U5 74VHC04 13 12 SPARES
11
10
U5 74VHC04
C26 0.1F
C24 1nF
Figure 92. Converter Schematic, TGC Using an AD8332 and AD9238
Rev. E | Page 36 of 40
03199-092
+3.3VADDIG
AD8331/AD8332/AD8334
DATACLKA 20 U10 VCC 74VHC541 19 10 G2 GND 2 18 A1 Y1 3 17 Y2 A2 16 4 Y3 A3 G1 5 6 7 8 9 A4 A5 A6 A7 A8 Y4 Y5 Y6 Y7 Y8 15 14 13 12 11 1 +3.3VDVDD R40 22 2
1 2 3 4 1 2 3 4 1 2 3 22 x 4 RP 3 22 x 4 RP2 22 x 4 RP 1 8 7 6 5 8 7 6 5 8 7 6 5 22 x 4 RP 4 8 7 6 5
+ C3 0.1F
1
22 x 4 RP 9
C28 10F 6.3V
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
HEADER UP MALE NO SHROUD
8 7 6 5
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
OTR_A D11_A D10_A D9_A D8_A D7_A D6_A
2 3 4 1 2 3 4
22 x 4 RP 10
8 7 6 5
+3.3VDVDD 1 19 D5_A D4_A D3_A D2_A D1_A D0_A DNC DNC
1 2 3 4 1 2 3 4 22 x 4 RP 12 22 x 4 RP 11 8 7 6 5 8 7 6 5
U7 VCC 20 74VHC541 10 G2 GND 2 18 A1 Y1 3 17 A2 Y2 G1 4 5 6 7 8 9 A3 A4 A5 A6 A7 A8 Y3 Y4 Y5 Y6 Y7 Y8 16 15 14 13 12 11
4
C8 0.1F
C10 + 0.1F
C76 10F 6.3V
1 2 3 4
SAM080UPM
+3.3VDVDD 1
1 22 x 4 RP 13 8 7 6 5 22 x 4 RP 14 8 7 6 5 22 x 4 8
19
OTR_B D11_B D10_B D9_B D8_B D7_B D6_B D5_B
2 3 4 1 2 3 4 1
20 U2 G1 VCC 74VHC541 10 GND G2 2 18 A1 Y1 3 17 A2 Y2 16 4 A3 Y3 5 15 A4 Y4 6 14 A5 Y5 7 13 A6 Y6 8 12 A7 Y7 9 11 A8 Y8
42 + C7 0.1F + C9 0.1F C27 10F 6.3V 44
1 2 3 4 1 2 3 4 1
41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79
03199-093
22 x 4 RP 5
8 7 6 5
46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 SAM080UPM
HEADER UP MALE NO SHROUD
22 x 4 RP 6
8 7 6 5
22 x 4 RP 7
8 7 6 5
+3.3VDVDD
RP 15
2 3
1
19 D4_B D3_B D2_B D1_B D0_B DNC DNC
2 3 4 1 2 3 4 22 x 4 RP 16 7 6 5 8 7 6 5
20 U3 VCC 74VHC541 10 GND G2 2 18 Y1 A1 G1 3 4 5 6 7 8 9 A2 A3 A4 A5 A6 A7 A8 Y2 Y3 Y4 Y5 Y6 Y7 Y8 17 16 15 14 13 12 11
C4 0.1F
C5 0.1F
C6 + 0.1F
C75 10F 6.3V
4 1 2 3 4
22 x 4 RP 8
8 7 6 5
R39 22
DATACLK
Figure 93. Interface Schematic, TGC Using an AD8332 and AD9238
Rev. E | Page 37 of 40
AD8331/AD8332/AD8334
CH 1 LNA INPUT
CH 2 LNA INPUT
64 COM2
63 COM1
62 INH1
61 LMD1
60 COM1X
59 LON1
58 LOP1
57 VIP1
56 VIN1
55 VPS1
54 GAIN12
53 CLMP12
52 EN12
51 EN34
50 VCM1
49 VCM2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
INH2
COM12 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 MODE NC COM34 VOH3 VOL3 VPS34 VOL4 VOH4
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CH 4 DIFFERENTIAL OUTPUT CH 3 DIFFERENTIAL OUTPUT CH 2 DIFFERENTIAL OUTPUT CH 1 DIFFERENTIAL OUTPUT
LMD2 COM2X LON2 LOP2 VIP2 VIN2 VPS2 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 GAIN34 COM4X INH3 CLMP34
AD8334
POWER SUPPLY DECOUPLING LOCATED ON WIRING SIDE
COM3
COM4
COM34 VCM4 VCM3
31 32
LMD4
LON4
LOP4
VPS4
HILO
INH4
VIN4
VIP4
CH 3 LNA INPUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30
CH 4 LNA INPUT
03199-094
Figure 94. Signal Path and Board Layout for AD8334
Rev. E | Page 38 of 40
NC
AD8331/AD8332/AD8334 OUTLINE DIMENSIONS
9.80 9.70 9.60
0.345 0.341 0.337
20
11
28
15
4.50 4.40 4.30
1 14
0.158 0.154 0.150
1
10
6.40 BSC
0.244 0.236 0.228
PIN 1
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8 0 0.75 0.60 0.45
0.010 0.004 COPLANARITY 0.004 0.065 0.049 0.069 0.053 8 0
SEATING PLANE
0.20 0.09
0.025 BSC
0.012 0.008
SEATING PLANE
0.010 0.006
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-153-AE
COMPLIANT TO JEDEC STANDARDS MO-137-AD
Figure 95. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters
Figure 96. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in Inches
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
12 MAX
9
0.25 MIN 3.50 REF THE EXPOSE PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
041806-A
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 97. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
Rev. E | Page 39 of 40
AD8331/AD8332/AD8334
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
*4.85 4.70 SQ 4.55
0.45 0.40 0.35
33 32
16 17
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF
THE EXPOSE PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 98. 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 9 mm x 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8331ARQ AD8331ARQ-REEL AD8331ARQ-REEL7 AD8331ARQZ 1 AD8331ARQZ-RL1 AD8331ARQZ-R71 AD8331-EVAL AD8332ACP-R2 AD8332ACP-REEL AD8332ACP-REEL7 AD8332ACPZ-R71 AD8332ACPZ-RL1 AD8332ARU AD8332ARU-REEL AD8332ARU-REEL7 AD8332ARUZ1 AD8332ARUZ-R71 AD8332ARUZ-RL1 AD8332-EVAL EVAL-AD8332/AD9238 AD8334ACPZ-WP1 AD8334ACPZ-REEL1 AD8334ACPZ-REEL71 AD8334-EVAL
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
-40C to +85C -40C to +85C -40C to +85C
Package Description 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) 20-Lead Shrink Small Outline Package (QSOP) Evaluation Board with AD8331ARQ 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) Evaluation Board with AD8332ARU Evaluation Board with AD8332ARU and AD9238 ADC 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board with AD8334ACP
Package Option RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 RQ-20 CP-32-2 CP-32-2 CP-32-2 CP-32-2 CP-32-2 RU-28 RU-28 RU-28 RU-28 RU-28 RU-28
CP-64-1 CP-64-1 CP-64-1
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03199-0-4/06(E)
Rev. E | Page 40 of 40
031706-A

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